Field of the Invention
The invention relates to a solid-state imaging device in which signal lines are closely arranged, a method of driving the solid-state imaging device, and an electronic device including such a solid-state imaging device.
Description of the Related Art
Complementary metal oxide semiconductor (CMOS) image sensors (CIS) have increasingly been used alternative to related-art charge coupled device (CCD) image sensors for attaining enhanced functionality and low power consumption.
Technology in reducing sizes of pixels and increasing the number of pixels has rapidly advanced in the field of recent CMOS sensors or CIS. The CIS field has successfully employed advanced process technology for CMOS LSI to develop smaller pixels to overtake the CCD image sensor field, which has once preceded the CIS field in reducing sizes of pixels. The CIS employs, as compared to the CCD image sensor, more components in the pixel and operation thereof is not simple so that the CIS includes signal line arrangement in the pixel similar to that used in a metal layer for a logic circuit. However, since incident paths need preparing for light incident upon photodiodes (PDs) that are used as photoelectric conversion elements, signal lines may have to be closely arranged in a limited area. If the number of pixels is increased in such a configuration, not only may the signal lines need elongating, but distances between adjacent signal lines, where signals are transmitted, may also need increasing. Consequently, the resistance of the signal line and the capacitance between the signal lines are both likely to increase, thereby increasing occurrence of signal crosstalk between signal lines adjacent to one another.
The crosstalk occurred in a case where a distance between the signal lines adjacent to each other is short is described with reference to FIG. 1.
FIG. 1 shows two signal lines arranged in the row direction in a solid-state imaging device; in which the upper signal line 100 indicates one of a transfer signal line, selection signal line, and reset signal line whereas the lower signal line 101 indicates an adjacent signal line adjacently arranged to the upper signal line 100. As shown in FIG. 1, if the signal lines 100 and 101 are adjacently arranged to each other, the resistance R increases at a portion distant from a driver circuit 102, and the capacitance C also increases between the signal lines 100 and 101. Thereafter, when a desired pulse signal φSig is input from the driver circuit 102 to the upper signal line 100, a differential component of the pulse signal φSig (differential pulse) is generated in the adjacent signal line 101. If the differential pulse generated is transmitted to turn ON the OFF-state transfer gate in the signal line 101, crosstalk occurs in the originally undriven signal line 101. This phenomenon is called “crosstalk”. If the signal line 101, which is being affected by the crosstalk, is a transfer signal line, in particular, the signal charge will be leaked from the photodiode.
In order to control the crosstalk occurred between the signal lines, it may be necessary to reduce the resistance R and the capacitance C between the signal lines. However, it is unpreferable to use a method in which the resistance R and the capacitance C between the signal lines are lowered by increasing the width of each of the signal lines or increasing the distance between the signal lines, because the method prevents rays of light from gathering to the photodiode which is used as a photoelectric conversion element. It is also undesirable to reduce output impedance of the driver circuit 102, because the resistance of signal line is too large to reduce the output impedance, thereby exhibiting no effect thereof.
In view of the aforementioned method, there may be provided a method of increasing or decreasing the apparent signal line resistance R and apparent capacitance C between the signal lines, in which driver circuits are arranged at both ends of the signal lines 100, 101 so as to drive each of the signal lines 100, 101 from both sides thereof. With this method, since load acting on each of the driver circuits are reduced by half, the signal line resistance R and the capacitance C between the signal lines can both be lowered.
However, in a case where the driver circuits are arranged at both ends of the signal lines 100, 101, control signals input to the driver circuits may need synchronizing. If the control signals are unsynchronized, transition of signals will be delayed. Specifically, in the use of CMOS driver circuits therefor, the method is particularly unpreferable to be used, because significantly unsynchronized control signals from both ends may result in the signal charge leakage.
In view of the aforementioned signal charge leakage due to the unsynchronized control signals, Japanese Unexamined Patent Application Publication No. 2006-217905 discloses a method of controlling output impedance, specifically, to control crosstalk that occurs between the signal lines. The publication discloses a circuit configuration to control the impedance of a terminal transistor, in which the crosstalk is lowered by reusing an original signal provided from one end of the signal line. In this configuration, the impedance of the terminal transistor is set to be low when other signals are input using the feedback of the original signal provided from one end of the signal line. The signal electric potential in the signal line is secured due to lowered impedance of the terminal transistor. Thus, signal fluctuation due to crosstalk can be inhibited.